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FPGA/ASIC Design and Verification Services

With regards to design and verification, Space R   acknowledges the distinct differences between research projects, commercial products, and government missions.  We have 30+ years of experience and have lead development efforts spanning each of the three fields. 

Our superior design flow includes:

  • Following strict design rules; specifically for synchronous systems

  • Management of clock trees and clock domain crossings

  • Avoidance and control of metastability effects

  • Avoidance of timing violations (setup, hold, and general race conditions)

  • Proper use of timing analysis tools

  • Evaluation of power distribution (potential hotspots, power budget compliance, and side channel analysis)

  • Attention to established design flow and compliance restrictions.

  • Establishing and defining novel methodologies for mitigation insertion.  Mitigation strategies take into account the unique characteristics and susceptibilities of the target system, mission/product requirements, and engineering feasibility. 


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