FPGA/ASIC Design and Verification Services
With regards to design and verification, Space R acknowledges the distinct differences between research projects, commercial products, and government missions. We have 30+ years of experience and have lead development efforts spanning each of the three fields.
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Our superior design flow includes:
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Following strict design rules; specifically for synchronous systems
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Management of clock trees and clock domain crossings
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Avoidance and control of metastability effects
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Avoidance of timing violations (setup, hold, and general race conditions)
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Proper use of timing analysis tools
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Evaluation of power distribution (potential hotspots, power budget compliance, and side channel analysis)
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Attention to established design flow and compliance restrictions.
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Establishing and defining novel methodologies for mitigation insertion. Mitigation strategies take into account the unique characteristics and susceptibilities of the target system, mission/product requirements, and engineering feasibility.